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WM9703 ac?97 revision 2.1 audio codec wolfson microelectronics ltd w :: www.wolfsonmicro.com production data, september 2001, rev 3.5 copyright ? 2001 wolfson microelectronics ltd. description WM9703 is a high-quality stereo audio codec compliant with the ac?97 revision 2.1 specification. it performs full duplex 18-bit codec functions and supports variable sample rates from 8 to 48k samples/s and offers excellent quality with high snr. additional features include 3d sound and line-level outputs. in addition, support is provided for variable sample rates and accommodation is made for master/slave mode operation. WM9703 is interchangeable with ac?97 codecs from wolfson and other suppliers. the WM9703 is fully operable on 3.3v or 5v or mixed 3.3/5v supplies, and is packaged in the industry standard 48-pin tqfp package with 7mm-body size. ac?97 features ? 3.3v or 5v operation ? 18-bit stereo codec ? s/n ratio > 95db ? multiple stereo input mixer ? mono and stereo volume control ? 48-pin tqfp package ? power management features ? low power implementation ? very low standby power ac?97 revision 2.1 features ? variable rate audio (vra) support ? analogue 3d stereo enhancement ? line level outputs ? supports revision. 2.1 specified modem sample rates and filtering ? master/slave id selection ? pc-beep connection when device held reset block diagram vol/ mute vol/ mute vol/ mute vol/ mute vol/ mute vol/ mute (37) monoout (39,41) lnlvlout (35,36) lineout cd (18,20) linein (23,24) video (16,17) aux (14,15) phone (13) pcbeep (12) mic[1] (21) mic[2] (22) 0db/ 20db master/ slave select (45) cid[0] (46) cid[1] (6) bitclk (10) sync (8) sdatain (5) sdataout (11) resetb (47) eapd vol/ mute osc (2) xtlin (3) xtlout vol stereo dac src 3d vol stereo adc src vol/ mute mux vol/ mute vol/ mute mux key: mono stereo record mux and mute serial i/f WM9703
WM9703 production data pd rev 3.5 september 2001 2 pin configuration ordering information device temp. range package WM9703cft/v 0 to 70 o c 48-pin tqfp 24 23 16 17 18 19 20 21 22 13 14 15 37 47 46 45 44 43 42 41 40 39 38 48 1 9 8 7 6 5 4 3 2 12 11 10 25 31 30 29 28 27 26 36 35 34 33 32 lineinr cdl mic2 cdgnd cdr mic1 lineinl auxr phone auxl videol videor dvdd1 dvss2 bitclk sdataout dvss1 xtlout xtlin sdatin dvdd2 sync resetb pcbeep nc nc nc cid0 cid1 eapd monoout avdd2 lnlvloutl nc lnlvloutr avss2 lineoutr nc cap1 cap2 cx3d1 cx3d2 lineoutl avdd1 avss1 vref vrefout afilt1 WM9703 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electri cal characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. as per specifications ipc/jedec j-std-020a and jedec a113-b, this product requires specific storage conditions prior to surface mount assembly. it has been classified as having a moisture sensitivity level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags. condition min max digital supply voltage -0.3v +7v analogue supply voltage -0.3v +7v voltage range digital inputs dvss -0.3v dvdd +0.3v voltage range analogue inputs avdd -0.3v avdd +0.3v operating temperature range, t a 0 o c+70 o c storage temperature -65 o c +150 o c package body temperature (soldering 10 seconds) +240 o c package body temperature (soldering 2 minutes) +183 o c note: 1. the digital supply voltage (dvdd) must always be less than or equal to the analogue supply voltage (avdd).
WM9703 production data pd rev 3.5 september 2001 3 recommended operating conditions parameter symbol test conditions min typ max unit digital supply range dvdd1, dvdd2 -10% 3.3 to 5.0 +10% v analogue supply range avdd1, avdd2 -10% 3.3 to 5.0 +10% v digital ground dvss1, dvss2 0 v analogue ground avss1, avss2 0 v difference dvss to avss -0.3 0 +0.3 v analogue supply current dvdd, avdd = 5v 35 ma digital supply current dvdd, avdd = 5v 25 ma standby supply current (all prs set) dvdd, avdd = 5v 10 a analogue supply current dvdd, avdd = 3.3v 22 ma digital supply current dvdd, avdd = 3.3v 15 ma standby supply current (all prs set) dvdd, avdd = 3.3v 6 a note: 1. both supplies should be powered on and off at the same time electrical characteristics test characteristics : avdd = 5v, gnd = 0v ????..t a = 0 o c to +70 o c, unless otherwise stated dvdd = 3.3v, gnd = 0v ????..t a = 0 o c to +70 o c, unless otherwise stated parameter symbol test conditions min typ max unit digital logic levels (dvdd = 3.3 or 5.0v) input low level v il avss -0.3 0.8 v input high level v ih 2.2 avdd +0.3 v output low v ol 0.1 x dvdd v output high v oh 0.9 x dvdd v analogue i/o levels (input signals on any inputs, outputs on lineout l, r and monoout) input level minimum input impedance = 10k avss -100mv avdd +100mv v output level into 10kohm load avss +100mv near rail to rail avdd -100mv v reference levels reference input/output cap2 2/5 avdd avdd/2 3/5 avdd v cap2 impedance 75 kohms mixer reference vref buffered cap2 v mic reference vrefout buffered cap2 v adc reference cap1 buffered cap2 v dac reference afilt1 buffered cap2 v midbuff current sink (pins cap1, afilt2, vref and vrefout) avdd = 5v -5 -15 ma midbuff current source (pins cap1, afilt1, vref and vrefout) avdd = 5v 5 15 ma midbuff current source (pins cap1, afilt1, vref and vrefout) avdd = 3.3v 5 ma
WM9703 production data pd rev 3.5 september 2001 4 test characteristics : avdd = 5v, gnd = 0v ????..t a = 0 o c to +70 o c, unless otherwise stated dvdd = 3.3v, gnd = 0v ????..t a = 0 o c to +70 o c, unless otherwise stated parameter symbol test conditions min typ max unit dac circuit specifications (avdd = 5v) 48khz sampling snr a-weighted (note 1) 85 96 db full scale output voltage vref = 2.5v 1.0 vrms thd -3dbfs input 74 90 db frequency response 20 19,200 hz transition band 19,200 28,800 hz stop band 28,800 hz out of band rejection -40 db spurious tone reduction -100 db psrr 20 to 20khz 40 db adc circuit specifications (avdd = 5v) 48khz sampling snr a-weighted (note 1) 75 85 db adc input for full scale output vref = 2.5v 1.0 vrms thd -6dbv input 74 90 db frequency response 20 19,200 hz transition band 19,200 28,800 hz stop band 28,800 hz stop band rejection -74 db psrr 20 to 20khz 40 db mixer circuit specifications (avdd = 5v) 48khz sampling snr cd path a-weighted (note 1) 90 100 db snr other paths a-weighted (note 1) 85 95 db maximum input voltage avss 1.0 avdd vrms maximum output voltage on lineout 1.0 1.8 vrms thd 0dbv input 74 90 db frequency response (+/-1db) 20 20,000 hz input impedance (cd inputs) at any gain 10 15 kohm at max gain 10 20 kohm input impedance (other mixer inputs) at 0db gain 100 kohm at max gain 80 kohm input impedance mic inputs at 0db gain 10 15 kohm psrr 20 to 20khz 40 db dac circuit specifications (avdd = 3.3v) 48khz sampling snr a-weighted (note 1) 96 db full scale output voltage vref = 1.65v 0.7 vrms thd 3dbfs input 90 db frequency response 20 19,200 hz transition band 19,200 28,800 hz stop band 28,800 hz out of band rejection -40 db spurious tone reduction -100 db psrr 20 to 20khz 40 db
WM9703 production data pd rev 3.5 september 2001 5 test characteristics : avdd = 5v, gnd = 0v ????..t a = 0 o c to +70 o c, unless otherwise stated dvdd = 3.3v, gnd = 0v ????..t a = 0 o c to +70 o c, unless otherwise stated parameter symbol test conditions min typ max unit adc circuit specifications (avdd = 3.3v) 48khz sampling snr a-weighted (note 1) 82 db adc input for full scale output vref = 1.65v 0.7 vrms thd -9dbv input 80 db frequency response 20 19,200 hz transition band 19,200 28,800 hz stop band 28,800 hz stop band rejection -74 db psrr 20 to 20khz 40 db mixer circuit specifications (avdd = 3.3v) 48khz sampling snr cd path a-weighted (note 1) 97 db snr other paths a-weighted (note 1) 92 db maximum input voltage 0.7 vrms maximum output voltage on lineout 0.7 vrms thd -3dbv input 90 db frequency response (+/-1db) 20 20,000 hz input impedance (cd inputs) at any gain 15 kohm at max gain 20 kohm input impedance (other mixer inputs) at 0db gain 100 kohm at max gain 80 kohm input impedance mic inputs at 0db gain 15 kohm psrr 20 to 20khz 40 db clock frequency range crystal clock 24.576 mhz bit_clk frequency 12.288 mhz sync frequency 48.0 khz note: 1. snr is the ratio of 0db signal output level to the output level with no signal, measured a-weighted over a 20hz to 20khz bandwidth.
WM9703 production data pd rev 3.5 september 2001 6 pin description pin name type description 1 dvdd1 supply digital positive supply 2 xtlin digital input clock crystal connection or clock input (xtal not used) 3 xtlout digital output clock crystal connection 4 dvss1 supply digital ground supply 5 sdataout digital input serial data input 6 bitclk digital output (master) digital input (slave) serial interface clock output to ac?97 controller or input from ac?97 master codec 7 dvss2 supply digital ground supply 8 sdatain digital output serial data output to ac?97 controller 9 dvdd2 supply digital positive supply 10 sync digital input serial interface sync pulse from ac?97 controller 11 resetb digital input not reset input (active low, resets registers) 12 pcbeep analogue input mixer input, typically for pcbeep signal 13 phone analogue input mixer input, typically for phone signal 14 auxl analogue input mixer input, typically for aux signal 15 auxr analogue input mixer input, typically for aux signal 16 videol analogue input mixer input, typically for video signal 17 videor analogue input mixer input, typically for video signal 18 cdl analogue input mixer input, typically for cd signal 19 cdgnd analogue input cd input common mode reference (ground) 20 cdr analogue input mixer input, typically for cd signal 21 mic1 analogue input mixer input with extra gain if required 22 mic2 analogue input mixer input with extra gain if required 23 lineinl analogue input mixer input, typically for line signal 24 lineinr analogue input mixer input, typically for line signal 25 avdd1 supply analogue positive supply 26 avss1 supply analogue ground supply, chip substrate 27 vref analogue output buffered cap2 28 vrefout analogue output reference for microphones; buffered cap2 29 nc no internal connection 30 nc no internal connection 31 nc no internal connection 32 cap2 analogue input reference input/output; pulls to midrail if not driven 33 cx3d1 analogue output output pin for 3d difference signal 34 cx3d2 analogue input input pin for 3d difference signal 35 lineoutl analogue output main analogue output for left channel 36 lineoutr analogue output main analogue output for right channel 37 monoout analogue output main mono output 38 avdd2 supply analogue positive supply 39 lnlvloutl analogue output left channel line level output 40 nc no internal connection 41 lnlvloutr analogue output right channel line level output 42 avss2 supply analogue ground supply, chip substrate 43 nc no internal connection 44 nc no internal connection 45 cid0 digital input master/slave id select (internal pull-up) 46 cid1 digital input master/slave id select (internal pull-up) 47 eapd digital output external amplifier powerdown/gpo 48 nc no internal connection note: 1 pins 27, 29 and 31 have an internal connection.
WM9703 production data pd rev 3.5 september 2001 7 detailed timing diagrams test characteristics : avdd = 5v, gnd = 0v ????..t a = 0 o c to +70 o c, unless otherwise stated. dvdd = 3.3v, gnd = 0v ????..t a = 0 o c to +70 o c, unless otherwise stated. all measurements are taken at 10% to 90% vdd, unless otherwise stated. ac-link low power mode sync bit_clk sdata_out write to 0x20 data pr4 don't care sdata_in slot 1 slot 2 t s2_pdown figure 1 ac-link powerdown timing parameter symbol min typ max unit end of slot 2 to bitclk sdatin low t s2_pdown 1.0 s cold reset resetb bit_clk t rst_low t rst2clk figure 2 cold reset timing parameter symbol min typ max unit resetb active low pulse width t rst_low 1.0 s resetb inactive to bit_clk start-up delay t rst2_clk 162.8 ns
WM9703 production data pd rev 3.5 september 2001 8 warm reset sync bit_clk t sync_high t sync2clk figure 3 warm reset timing parameter symbol min typ max unit sync active high pulse width t sync_high 1.3 s sync inactive to bit_clk start- up delay t sync2_clk 162.4 ns clock specifications bit_clk sync t clk_high t clk_low t clk_period t sync_high t sync_low t sync_period figure 4 clock specifications (50pf external load) note: worst case duty cycle restricted to 40/60. parameter symbol min typ max unit bit_clk frequency 12.288 mhz bit_clk period t clk_period 81.4 ns bit_clk output jitter 750 ps bit_clk high pulse width (note 1) t clk_high 32.56 40.7 48.84 ns bit_clk low pulse width (note 1) t clk_low 32.56 40.7 48.84 ns sync frequency 48.0 khz sync period t sync_period 20.8 s sync high pulse width t sync_high 1.3 s sync low pulse width t sync_low 19.5 s
WM9703 production data pd rev 3.5 september 2001 9 data setup and hold (50pf external load) bit_clk sdata_out sync t setup t hold figure 5 data setup and hold (50pf external load) note: setup and hold time parameters for sdata_in are with respect to ac?97 controller. parameter symbol min typ max unit setup to falling edge of bit_clk t setup 15.0 ns hold from falling edge of bit_clk t hold 5.0 ns signal rise and fall times bit_clk sync sdata_in sdata_out t rise clk t fall clk t rise sync t fall sync t rise din t fall din t rise dout t fall dout figure 6 signal rise and fall times (50pf external load) parameter symbol min typ max unit bit_clk rise time trise clk 26ns bit_clk fall time tfall clk 26ns sync rise time trise sync 26ns sync fall time tfall sync 26ns sdata_in rise time trise din 26ns sdata_in fall time trise din 26ns sdata_out rise time trise dout 26ns sdata_out fall time tfall dout 26ns
WM9703 production data pd rev 3.5 september 2001 10 system information WM9703 ac'97 digital controller reset bitcl k sync sdatai n sdataou t cid0 cid1 { chip select pcbeep phone cd, video, aux, lineinl/ r monoout { lnlvloutl/r lineoutl/r mic2 mic1 37 41 39 36 13 12 21 22 11 6 10 8 5 45 46 35 figure 8 revision 2.1 compliant 2-channel codec sdataout bitclk sdatain sync reset WM9703 front r data front l data lineoutl lineoutr id=00 sdataout bitclk sdatain sync reset WM9703 surround r data surround l data lineoutl lineoutr id=10 sdataout bitclk sdatain sync reset xtlout xtlin pc i/o chipset or ac'97 controller figure 9 WM9703 in a 4 channel system
WM9703 production data pd rev 3.5 september 2001 11 sdataout bitclk sdatain sync reset WM9703 front r data front l data lineoutl lineoutr id=00 sdataout bitclk sdatain sync reset WM9703 surround r data surround l data lineoutl lineoutr id=10 sdataout bitclk sdatain sync reset WM9703 centre data lfe data lineoutl lineoutr id=11 sdataout bitclk sdatain sync reset xtlout xtlin xtlin pc i/o chipset or ac'97 controller figure 10 WM9703 in a 6 channel system sdataout bitclk sdatain sync resetb docking station notebook/ laptop WM9703 sdataout bitclk sdatain sync resetb lineoutl lineoutr WM9703 sdataout bitclk sdatain sync resetb id=00 id=00 option of using resetb or sdatain to disable nb codec when docked. cid1 cid0 if pins cid0/1 not driven then codec id defaults to 00. when docked cid1 is pulled low making codec a 'slave' (01) stopping bitclk pc i/o chipset or ac'97 controller figure 11 WM9703 in a docking station system
WM9703 production data pd rev 3.5 september 2001 12 device description introduction the WM9703 is fully compliant with revision 2.1 of the ac?97 specification. the WM9703 comprises a stereo 18-bit codec, (that is, 2 adcs and 2 dacs) plus a comprehensive analogue mixer with 4 sets of stereo inputs, plus phone, 2 microphone, and pc-beep inputs. additionally, on-chip reference generation circuits generate the necessary bias voltages for the device, and a bidirectional serial interface allows transfer of control data and dac and adc words to and from the ac?97 controller. the WM9703 supports 18-bit resolution within the dac and adc functions, but the ac?97 serial interface specification allows any word length up to 20-bits to be written to, or read from, the ac?97 codec. these words are msb justified, and any lsbs not used will simply default to 0. normally it is anticipated that 16-bit words will be used in most pc type systems. therefore, for the dac, 16-bit words will be downloaded into the codec from the controller, along with padding of 0s to make the 16-bit word up to 20-bit length. in this case, the WM9703 will process the 16-bit word along with 0 padding bits in the 2 lsb locations (to make 18-bit). at the adc output, WM9703 will provide an 18-bit word, again with 0s in the two lsb locations (20-bit). the ac?97 controller will then ignore the 4 lsbs of the 20-bit word. when the WM9703 is interrogated, it responds indicating it is an 18-bit device. the WM9703 has the adc and dac functions implemented using oversampled, or sigma-delta converters, and uses on-chip digital filters to convert these 1-bit signals to and from the 48ks/s 16/18-bit pcm words that the ac?97 controller requires. the digital parts of the device are powered separately from the analogue to optimise performance and 3.3v digital and 5v analogue supplies may be used on the same device to further optimise performance. digital ios are 5v tolerant when the analogue supplies are 5v, so the WM9703 may be connected to a controller running on 5v supplies, but use 3.3v for the digital section of WM9703. WM9703 is also capable of operating with a 3.3v supply only (digital and analogue). an internally generated midrail reference is provided at pin cap2 which is used as the chip reference. this pin should be heavily decoupled. the WM9703 is not limited to pc-only applications. the ability to powerdown sections of the device selectively, and the option to choose alternative master clock, and hence sample rates, means that many alternative applications in areas such as telecomms, may be anticipated. additional features added to the intel ac?97 specification, such as the eapd (external amplifier power down) bit, internal connection of pc-beep to the outputs in the case where the device is reset, are supported, along with optional features such as variable sample rate support. 3d stereo enhancement this device contains a stereo enhancement circuit, designed to optimise the listening experience when the device is used in a typical pc operating environment. that is, with a pair of speakers placed either side of the monitor with little spatial separation. this circuit creates a difference signal by differencing left and right channel playback data, then filters this difference signal using lowpass and highpass filters whose time constants are set using external capacitors connected to the cx3d pins 33 and 34. typically the values of 100nf and 47nf set highpass and lowpass poles at about 100hz and 1khz respectively. this frequency band corresponds to the range over which the ear is most sensitive to directional effects. the filtered difference signal is gain adjusted by an amount set using the 4-bit value written to register 22h bits 3 to 0. value 0h is disable, value fh is maximum effect. typically a value of 8h is optimum. the user interface would most typically use a slider type of control to allow the user to adjust the level of enhancement to suit the program material. bit d13 3d in register 20h is the overall 3d enable bit. the capability register 00h reads back the value 11000 in bits d14 to d10. this corresponds to decimal 24, which is registered with intel as wolfson stereo enhancement. note that the external capacitors setting the filtering poles applied to the difference signal may be adjusted in value, or even replaced with a direct connection between the pins. if such adjustments are made, then the amount of difference signal fed back into the main signal paths may be significant, and can cause large signals which may limit, distort, or overdrive signal paths or speakers. adjust these values with care, to select the preferred acoustic effect. there is no provision for pseudo-stereo effects. mono signals will have no enhancement applied (if the signals are in phase and of the same amplitude).
WM9703 production data pd rev 3.5 september 2001 13 signals from the pcm dac channels do not have stereo enhancement applied. it is assumed that these signals will already have been processed digitally with any required 3d enhancement effect. applying the analogue 3d enhancement will corrupt this digital effect. this is equivalent to setting the pop bit in register 20h. as a result, the readback value of this bit is fixed as 1, and attempts to change it will be ignored. pop bit is set to one and cannot be re-set. variable sample rate support the dacs and adcs on this device support all the recommended sample rates specified in the intel revision 2.1 specification for both audio and modem rates. default rates are 48ks/s. if alternative rates are selected, the ac?97 interface continues to run at 48k words per second, but data is transferred across the link in bursts such that the net sample rate selected is achieved. it is up to the ac?97 revision 2.1 compliant controller to ensure that data is supplied to the ac link, and received from the ac link, at the appropriate rate. the device supports on demand sampling. that is, when the dac signal processing circuits need another sample, a sample request is sent to the controller which must respond with a data sample in the next frame it sends. for example, if a rate of 24ks/s is selected, on average the device will request a sample from the controller every other frame, for each of the stereo dacs. note that if an unsupported rate is written to one of the rate registers, the rate will default to the nearest rate supported. the register will then respond when interrogated with the supported rate the device has defaulted to. adcs are controlled similarly but with one difference: normally the left and right channel adcs sample at the same rate. audio sample rate control value d15-d0 modem sample rate control value d15-d0 8000 1f40 7200 1c20 11025 2b11 8228.57 (57600/7) 2024 16000 3e80 8400 20d0 22050 5622 9000 2328 44100 ac44 9600 2580 48000 bb80 10285.71 (72000/7) 282d 12000 2ee0 13714.28 (96000/7) 3592 19200 4b00 24000 5dc0 table 3 variable sample rates supported the following table shows which registers control which dac rates, versus mode and id selected codec id front dac rate register adc rate reg 00 and 01 2ch 10 2eh 11 2ch (centre) and 30h (lfe) 32h table 4 variable rate register location versus id
WM9703 production data pd rev 3.5 september 2001 14 gain control register location versus id pga codec id control reg mute default dac 0x 10 11 18h muted (bit-15) and with 38h, 7, 15 and with 36h, 7, 15 mixer 0x 10 11 72h not-muted (bit-15) volume 0x 10 11 02h 38h 36h muted (15) muted (7 and 15) muted (7 and15) table 5 gain control register location versus id master/slave id0/1 support WM9703 supports operation as either a master or a slave codec. configuration of the device as either a master or as a slave, is selected by tying the cid pins cid0 and cid1, pins 45 and 46 on the package. fundamentally, a device identified as a master (id = 00) produces bitclk as an output, whereas a slave (any other id) must be provided with bitclk as an input. this has the obvious implication that if the master device on an ac link is disabled, the slave devices cannot function. the ac?97 revision 2.1 specification defines that the cid pins have inverting sense, and are provided with internal weak pull ups. therefore, if no connections are made to the cid0/1 pins, then the pins pull hi and an id = 00 is selected, i.e. master. external connects to ground will select other ids. pin46 cid1 pin45 cid0 id selected master or slave bitclk nc nc 00 master output nc ground 01 slave input ground nc 10 slave input ground ground 11 slave input table 6 id selection WM9703 supports the amap function whereby selection of an id will automatically map the data from the interface onto the pcm dacs. this allows a 6-channel audio system to be built using 3 WM9703 devices, with one device configured as a master (id 00) and the other two as slaves (id 10 and 11). (see figure 10). in this case, the main channel dacs will have mapped onto them the data from the normal, surround, and lfe and centre slots respectively, without any user selection. codec id ac?link frame data used for dacs comments pcm left dac uses data from slot no. pcm right dac uses data from slot no. 00 3 4 original definition (master) 01 3 4 original definition (docking) 10 7 8 left/right surround channels 11 6 9 centre/lfe channels the codec id is available to the controller via register 28h, bits d15 and d14 table 7 default slot to dac mappings based on codec id codec id slots mapped to dacs 00 or 01 3 and 4 10 7 and 8 11 6 and 9 table 8 slot to dac and mapping based on codec id
WM9703 production data pd rev 3.5 september 2001 15 control interface a digital interface has been provided to control the WM9703 and transfer data to and from it. this serial interface is compatible with the intel ac?97. the main control interface functions are: ? control of analogue gain and signal paths through the mixer ? bi-directional transfer of adc and dac words to and from ac?97 controller ? selection of powerdown modes ac-link digital serial interface protocol the WM9703 incorporates a 5-pin digital serial interface that links it to the ac?97 controller. ac-link is a bi-directional, fixed rate, serial pcm digital stream. it handles multiple input and output audio streams, as well as control register accesses employing a time division multiplexed (tdm) scheme. the ac-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. with a minimum required dac and adc resolution of 16-bits, ac?97 may also be implemented with 18 or 20-bit dac/adc resolution, given the headroom that the ac-link architecture provides. the WM9703 provides support for 18-bit operation. slot number sync sdata_out sdata_in tag phase tag cmd adr cmd data pcm left pcm right rsrvd pcm lfe rsrvd rsrvd tag status addr status data pcm left pcm right rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd data phase 0123456789101112 pcm centre pcm l surr pcm r surr rsrvd pcm c (n+1) pcm r (n+1) pcm l (n+1) codec id slotreq 3-12 figure 12 ac?97 standard bi-directional audio frame sync bit_clk sdata_out valid frame slot(1) slot(2) slot(12) '0' (id1) (id0) 19 0 19 0 19 0 19 0 tag phase data phase 20.8 s (48khz) 12.288mhz 81.4ns end of previous audio frame time slot 'valid' bits ('1' = time slot contains valid pcm data) slot (1) slot (2) slot (3) slot (12) figure 13 ac-link audio output frame
WM9703 production data pd rev 3.5 september 2001 16 the datastreams currently defined by the ac?97 specification include: pcm playback - 2 output slots 2-channel composite pcm output stream pcm record data - 2 input slots 2-channel composite pcm input stream control - 2 output slots control register write port status - 2 input slots control register read port optional modem line codec output - 1 output slot modem line codec dac input stream optional modem line codec input ? 1 input slot modem line codec adc output stream optional dedicated microphone input - 1 input slot dedicated microphone input stream in support of stereo aec and/or other voice applications. synchronisation of all ac-link data transactions is signalled by the WM9703 controller. the WM9703 drives the serial bit clock onto ac-link, which the ac?97 controller then qualifies with a synchronisation signal to construct audio frames. sync, fixed at 48khz, is derived by dividing down the serial clock (bit_clk). bit_clk, fixed at 12.288mhz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. ac-link serial data is transitioned on each rising edge of bit_clk. the receiver of ac-link data, (WM9703 for outgoing data and ac?97 controller for incoming data), samples each serial bit on the falling edges of bit_clk. the ac-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. a 1 in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. if a slot is tagged invalid, it is the responsibility of the source of the data, (the WM9703 for the input stream, ac?97 controller for the output stream); to stuff all bit positions with 0s during that slot?s active time. sync remains high for a total duration of 16 bit_clks at the beginning of each audio frame. the portion of the audio frame where sync is high is defined as the tag phase. the remainder of the audio frame where sync is low is defined as the data phase. additionally, for power savings, all clock, sync, and data signals can be halted. this requires that the WM9703 be implemented as a static design to allow its register contents to remain intact when entering a power savings mode. ac-link audio output frame (sdata_out) the audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting the WM9703?s dac inputs, and control registers. as briefly mentioned earlier, each audio output frame supports up to 12 20-bit outgoing data time slots. slot 0 is a special reserved time slot containing 16-bits, which are used for ac-link protocol infrastructure. output tag slot (16-bits) bit (15) frame valid bit (14) slot 1 valid command address bit (primary codec only) bit (13) slot 2 valid command data bit (primary codec only) bit (12:3) slot 3-12 valid bits as defined by ac?97 bit 2 reserved (set to 0) bit (1:0) 2-bit codec id field (00 reserved for primary; 01, 10, 11 indicate secondary) new definitions for secondary codec register access within slot 0 the first bit is a global bit (sdata_out slot 0, bit 15) which flags the validity for the entire audio frame. if the valid frame bit is a 1, this indicates that the current audio frame contains at least one time slot of valid data. the next 12-bit positions sampled by the WM9703 indicate which of the corresponding 12 time slots contain valid data. in this way data streams of differing sample rates can be transmitted across ac-link at its fixed 48khz audio frame rate. figure 13 illustrates the time slot based ac-link protocol.
WM9703 production data pd rev 3.5 september 2001 17 sync bit_clk sdata_out valid frame slot (1) slot (2) WM9703 samples sync assertion here WM9703 samples first sdata_out bit of frame here end of previous audio frame figure 14 start of an audio output frame a new audio output frame begins with a low to high transition of sync as shown in figure 14. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the WM9703 samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising edge of bit_clk, ac?97 transitions sdata_out into the first bit position of slot 0 (valid frame bit). each new bit position is presented to ac-link on a rising edge of bit_clk, and subsequently sampled by the WM9703 on the following falling edge of bit_clk. this sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. baseline ac?97 specified audio functionality must always sample rate convert to and from a fixed 48ks/s on the ac?97 controller. this requirement is necessary to ensure that interoperability between the ac?97 controller and the WM9703, among other things, can be guaranteed by definition for baseline specified ac?97 features. sdata_out?s composite stream is msb justified (msb first) with all non-valid slot bit positions stuffed with 0s by the ac?97 controller. in the event that there are less than 20 valid bits within an assigned and valid time slot, the ac?97 controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0s. as an example, consider an 8-bit sample stream that is being played out to one of the WM9703?s dacs. the first 8 bit positions are presented to the dac (msb justified) followed by the next 12 bit positions, which are stuffed with 0s by the ac?97 controller. this ensures that regardless of the resolution of the implemented dac (16, 18 or 20-bit), no dc biasing will be introduced by the least significant bits. when mono audio sample streams are output from the ac?97 controller, it is necessary that both left and right sample stream time slots be filled with the same data. slot 1: command address port the command port is used to control features, and monitor status for the WM9703 functions including, but not limited to, mixer settings, and power management (refer to the register section). the control interface architecture supports up to 64, 16-bit read/write registers, addressable on even byte boundaries. only the even registers (00h, 02h, etc.) are valid, odd register (01h, 03h, etc.) accesses are discouraged (if supported they should default to the preceding even byte boundary - i.e. a read to 01h will return the 16-bit contents of 00h). the WM9703?s control register file is nonetheless readable as well as writeable to provide more robust testability. audio output frame slot 1 communicates control register address, and read/write command information to the WM9703. command address port bit assignments bit (19) read/write command (1 = read, 0 = write) bit (18:12) control register index (64 16-bit locations, addressed on even byte boundaries) bit (11:0) reserved (stuffed with 0s) the first bit (msb) sampled by the WM9703 indicates whether the current control transaction is a read or write operation. the following 7 bit positions communicate the targeted control register
WM9703 production data pd rev 3.5 september 2001 18 address. the trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by the ac?97 controller. slot 2: command data port the command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle. (as indicated by slot 1, bit 19). bit (19:4) control register write data (stuffed with 0s if current operation is a read) bit (3:0) reserved (stuffed with 0s) if the current command port operation is a read then the entire time slot must be stuffed with 0s by the ac?97 controller. slot 3: pcm playback left channel audio output frame slot 3 is the composite digital audio left playback stream. in a typical games compatible pc this slot is composed of standard pcm (.wav) output samples digitally mixed (on the ac?97 controller or host processor) with music synthesis output samples. if a sample stream of resolution less than 20-bits is transferred, the ac?97 controller must stuff all trailing non-valid bit positions within this time slot with 0s. slot 4: pcm playback right channel audio output frame slot 4 is the composite digital audio right playback stream. in a typical games compatible pc this slot is composed of standard pcm (.wav) output samples digitally mixed (on the ac?97 controller or host processor) with music synthesis output samples. if a sample stream of resolution less than 20-bits is transferred, the ac?97 controller must stuff all trailing non-valid bit positions within this time slot with 0s. slot 5: optional modem line codec audio output frame slot 5 contains the msb justified modem dac input data. this optional ac?97 feature is not supported in the WM9703, and if data is written to this location it is ignored. this may be determined by the ac?97 controller interrogating the WM9703 vendor id registers. slots 6 to 9: surround sound data audio output frame slots 6 to 9 are used to send surround sound data. this data is mapped onto the internal dacs depending on codec id, see table 8. slots 10 and 11: line2 and handset dac these data slots are not supported. slot 12: gpio control these data slots are not supported. ac-link audio input frame (sdata_in) sync bit_clk sdata_in codec ready slot(1) slot(2) slot(12) '0' '0' '0' 19 0 19 0 19 0 19 0 tag phase data phase 20.8 s (48khz) 12.288mhz 81.4ns end of previous audio frame time slot 'valid' bits ('1' = time slot contains valid pcm data) slot (1) slot (2) slot (3) slot (12) figure 15 ac-link audio input frame
WM9703 production data pd rev 3.5 september 2001 19 the audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the ac?97 controller. as is the case for audio output frame, each ac-link audio input frame consists of 12, 20-bit time slots. slot 0 is a special reserved time slot containing 16-bits, which are used for ac-link protocol infrastructure. within slot 0 the first bit is a global bit (sdata_in slot 0, bit 15) which flags whether the WM9703 is in the codec ready state or not. if the codec ready bit is a 0, this indicates that the WM9703 is not ready for normal operation. this condition is normal following the desertion of power on reset for example, while the WM9703?s voltage references settle. when the ac-link codec ready indicator bit is a 1, it indicates that the ac-link and the WM9703 control and status registers are in a fully operational state. the ac?97 controller must further probe the powerdown control/status register to determine exactly which subsections, if any, are ready. prior to any attempts at putting the WM9703 into operation the ac?97 controller should poll the first bit in the audio input frame (sdata_in slot 0, bit 15) for an indication that the WM9703 has gone codec ready. once the WM9703 is sampled codec ready then the next 12 bit positions sampled by the ac?97 controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data. figure 15 illustrates the time slot based ac-link protocol. there are several subsections within the WM9703 that can independently go busy/ready. it is the responsibility of the WM9703 controller to probe more deeply into the WM9703 register file to determine which the WM9703 subsections are actually ready. sync bit_clk sdata_in codec ready slot (1) slot (2) WM9703 samples sync assertion here ac'97 controller samples first sdata_in bit of frame here end of previous audio frame figure 16 start of an audio input frame a new audio input frame begins with a low to high transition of sync as shown in figure 16. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, ac?97 samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising of bit_clk, ac?97 transitions sdata_in into the first bit position of slot 0 (?codec ready? bit). each new bit position is presented to ac-link on a rising edge of bit_clk, and subsequently sampled by the ac?97 controller on the following falling edge of bit_clk. this sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. sdata_in?s composite stream is msb justified (msb first) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0s by the WM9703. sdata_in should be sampled on the falling edges of bit_clk. slot 1: status address port the status port is used to monitor status for the WM9703 functions including, but not limited to, mixer settings, and power management. audio input frame slot 1 echoes the control register index, for historical reference, for the data to be returned in slot 2. (assuming that slots 1 and 2 had been tagged valid by the WM9703 during slot 0). status address port bit assignments : bit (19) reserved (stuffed with 0s) bit (18:12) control register index (echo of register index for which data is being returned)
WM9703 production data pd rev 3.5 september 2001 20 bit (11:2) variable sample rate slotreq bits. bit (1:0) reserved (stuffed with 0s) the first bit (msb) generated by the WM9703 is always stuffed with an 0. the following 7 bit positions communicate the associated control register address. the next 10 bits support the ac?97 rev 2.1 variable sample rate signalling protocol, and the trailing 2 bit positions are stuffed with 0s by ac?97. slot 2: status data port the status data port delivers 16-bit control register read data. bit (19:4) control register read data (stuffed with 0s if tagged invalid by wm9701) bit (3:0) reserved (stuffed with 0s) if slot 2 is tagged invalid by the WM9703, then the entire slot will be stuffed with 0s by the WM9703. slot 3: pcm record left channel audio input frame slot 3 is the left channel output of the WM9703?s input mux, post-adc. the WM9703 sends out its adc output data (msb first), and stuffs any trailing non-valid bit positions with 0s to fill out its 20-bit time slot. slot 4: pcm record right channel audio input frame slot 4 is the right channel output of the WM9703?s input mux, post-adc. the WM9703?s adcs can be implemented to support 16, 18, or 20-bit resolution. the WM9703 ships out its adc output data (msb first), and stuffs any trailing non-valid bit positions with 0s to fill out its 20-bit time slot. slot 5: optional modem line codec audio input frame slot 5 contains msb justified modem adc output data. this optional feature is not supported by WM9703. this may be determined by the ac?97 controller interrogating the WM9703 vendor id register. slot 6: optional dedicated microphone record data audio input frame slot 6 is an optional (post-adc) third pcm system, input channel available for dedicated use by a desktop microphone. this optional ac?97 feature is not supported by the WM9703. this may be determined by the ac?97 controller interrogating the WM9703 vendor id register. slots 7 to 12: reserved audio input frame slots 7 to 12 are reserved for future use and are always stuffed with 0s by the WM9703. ac-link low power mode the ac-link signals can be placed in a low power mode. when the WM9703?s powerdown register 26h, is programmed to the appropriate value, both bit_clk and sdata_in will be brought to, and held at a logic low voltage level. bit_clk and sdata_in are transitioned low immediately following the decode of the write to the powerdown register 26h with pr4. when the ac?97 controller driver is at the point where it is ready to program the ac-link into its low power mode, slots 1 and 2 are assumed to be the only valid stream in the audio output frame. at this point in time it is assumed that all sources of audio input have also been neutralised. the ac?97 controller should also drive sync and sdata_out low after programming the WM9703 to this low power, halted mode. once the WM9703 has been instructed to halt bit_clk, a special wake up protocol must be used to bring the ac-link to the active mode since normal audio output and input frames can not be communicated in the absence of bit_clk.
WM9703 production data pd rev 3.5 september 2001 21 waking up the ac-link there are 2 methods for bringing the ac-link out of a low power, halted mode. regardless of the method, it is the ac?97 controller that performs the wake up task. ac-link protocol provides for a cold WM9703 reset, and a warm WM9703 reset. the current powerdown state would ultimately dictate which form of WM9703 reset is appropriate. unless a cold or register reset (a write to the reset register) is performed, wherein the WM9703 registers are initialised to their default values, registers are required to keep state during all powerdown modes. once powered down, re-activation of the ac-link via re-assertion of the sync signal must not occur for a minimum of 4 audio frame times following the frame in which the powerdown was triggered. when ac-link powers up it indicates readiness via the codec ready bit (input slot 0, bit 15). cold WM9703 reset a cold reset is achieved by asserting resetb for the minimum specified time. by driving resetb low, bit_clk, and sdata_out will be activated, or re-activated as the case may be, and all the WM9703 control registers will be initialised to their default power on reset values. resetb is an asynchronous WM9703 input. warm WM9703 reset a warm WM9703 reset will re-activate the ac-link without altering the current WM9703 register values. a warm reset is signalled by driving sync high for a minimum of 1 s in the absence of bit_clk. within normal audio frames sync is a synchronous input. in the absence of bit_clk, sync is treated as an asynchronous input used in the generation of a warm reset to the WM9703. the WM9703 will not respond with the activation of bit_clk until sync has been sampled low again by the WM9703. this will preclude the false detection of a new audio frame. serial interface register map description (see table 21) the serial interface bits perform control functions described as follows: the register map is fully specified by the ac?97 specification, and this description is simply repeated below, with optional unsupported features omitted. reset register (index 00h) writing any value to this register performs a register reset, which causes all registers to revert to their default values. reading this register returns the id code of the part, indication of modem support (not supported by the WM9703) and a code for the type of 3d stereo enhancement. the id decodes the capabilities of the WM9703 based on the following: bit function value on WM9703 id0 dedicated mic pcm in channel 0 id1 modem line codec support 0 id2 bass and treble control 0 id3 simulated stereo (mono to stereo) 0 id4 headphone out support 1 id5 loudness (bass boost) support 0 id6 18-bit dac resolution 1 id7 20-bit dac resolution 0 id8 18-bit adc resolution 1 id9 20-bit adc resolution 0 se4...se0 wolfson microelectronics 3d enhancement 11000 table 9 reset register function note that the WM9703 defaults to indicate 18-bit compatibility. however, a control bit may be set in the vendor-specific registers that changes bits id6 and id8 to be 0, indicating a 16-bit device. it is unlikely that this function will be required, however, as the msb justification of the adc and dac
WM9703 production data pd rev 3.5 september 2001 22 data means that a nominally 18-bit device should be fully compatible with controllers that only provide 16-bit support. most pc type applications will only require 16-bit operation. play master volume registers (index 02h, 04h and 06h) these registers manage the output signal volumes. register 02h controls the stereo master volume (both right and left channels), register 04h controls the optional stereo headphone out, and register 06h controls the mono volume output. each step corresponds to 1.5db. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. ml5 to ml0 is for left channel level, mr5 to mr0 is for the right channel and mm5 to mm0 is for the mono out channel. support for the msb of the volume level is not provided by the WM9703. if the msb is written to, then the WM9703 detects when that bit is set and sets all 4 lsbs to 1s. example: if the driver writes a 1xxxxx the wm 9703 interprets that as x11111. it will also respond when read with x11111 rather than 1 xxxxx, the value written to it. the driver can use this feature to detect if s upport for the 6th bit is there or not. the default value of both the mono and the stereo registers is 8000h (1000 0000 0000 0000), which corresponds to 0db gain with mute on. mute mx4...mx0 function 0 0 0000 0db attenuation 0 0 0001 1.5db attenuation 0 1 1111 46.5db attenuation 1 x xxxx db attenuation table 10 volume register function master tone control registers (index 08h) optional register for support of tone controls (bass and treble). the WM9703 does not support bass and treble and writing to this register will have no effect. reading will result in all don?t care values. pc beep register (index 0ah) this controls the level for the pc-beep input. each step corresponds to approximately 3db of attenuation. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. WM9703 defaults to the pc-beep path being muted, so an external speaker should be provided within the pc to alert the user to power on self-test problems. mute pv3...pv0 function 0 0000 0db attenuation 0 1111 45db attenuation 1 xxxx db attenuation table 11 pc-beep register function analogue mixer input gain registers (index 0ch - 18h) this controls the gain/attenuation for each of the analogue inputs. each step corresponds to approximately 1.5db. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. register 0eh (mic volume register) this has an extra bit that is for a 20db boost. when bit 6 is set to 1 the 20db boost is on. the default value is 8008, which corresponds to 0db gain with mute on. the default value for the mono registers is 8008h, which corresponds to 0db gain with mute on. the default value for stereo registers is 8808h, which corresponds to 0db gain with mute on. mute gx4...gx0 function 0 00000 +12db gain 0 01000 0db gain 0 11111 -34.5db gain 1 xxxxx - db gain table 12 mixer gain control register function
WM9703 production data pd rev 3.5 september 2001 23
WM9703 production data pd rev 3.5 september 2001 24 record select control register (index 1ah) used to select the record source independently for right and left (see table 13). the default value is 0000h, which corresponds to mic in. sr2 to sr0 right record source sl2 to sl0 left record source 0 mic 0 mic 1 cd in (r) 1 cd in (l) 2 video in (r) 2 video in (l) 3 aux in (r) 3 aux in (l) 4 line in (r) 4 line in (l) 5 stereo mix (r) 5 stereo mix (l) 6 mono mix 6 mono mix 7 phone 7 phone table 13 record select register function record gain registers (index 1ch and 1eh) 1ch is for the stereo input and 1eh is for the optional special purpose correlated audio mic channel. each step corresponds to 1.5db. 22.5db corresponds to 0f0fh and 000fh respectively. the msb of the register is the mute bit. when this bit is set to 1, the level for that channel(s) is set at - db. the default value is 8000h, which corresponds to 0db gain with mute on. mute gx3...gx0 function 0 1111 +22.5db gain 0 0000 0db gain 1 xxxxx - db gain table 14 record gain register function general purpose register (index 20h) this register is used to control several miscellaneous functions of the WM9703. below is a summary of each bit and its function. only the 3d, mix, ms and lpbk bits are supported by the WM9703. the ms bit controls the mic selector. the lpbk bit enables loopback of the adc output to the dac input without involving the ac-link, allowing for full system performance measurements. the function default value is 8000h which is all off. bit function WM9703 support pop pcm out path and mute, 0 = pre-3d, 1 = post-3d yes, but fixed at 1 st simulated stereo enhancement, on/off 1 = on no 3d 3d stereo enhancement on/off, 1 = on yes ld loudness (bass boost) on/off, 1 = on no llbk local loop back - for modem, line codec no rlbk remote loop back - for modem, line codec no mix mono output select 0 = mix, 1 = mic yes ms mic select 0 = mic1, 1 = mic2 yes lpbk adc/dac/ loopback mode yes table 15 general purpose register function 3d control register (index 22h) this register is used to control the centre and/or depth of the 3d stereo enhancement function built into of the ac?97 component. only the depth bits, dp0 to 3 have effect in the WM9703. dp3?dp0 depth 00% 1 - 8 typical value -
WM9703 production data pd rev 3.5 september 2001 25 15 100% reserved register (index 24h) this register was originally specified to control what sample rate ac?97 is sending or receiving samples for the optional modem in and out. not supported by the WM9703. powerdown control/status register (index 26h) this read/write register is used to program powerdown states and monitor subsystem readiness. the lower half of this register is read only status, a 1 indicating that the subsection is ready . ready is defined as the subsection able to perform in its nominal state. when this register is written the bit values that come in on ac-link will have no effect on read only bits 0 to7. when the ac-link codec ready indicator bit (sdata_in slot 0, bit 15) is a 1 it indicates that the ac- link and the WM9703 control and status registers are in a fully operational state. the ac?97 controller must further probe this powerdown control/status register to determine exactly which subsections, if any, are ready. read bit function ref vrefs up to nominal level anl analogue mixers, etc ready dac dac section ready to accept data adc adc section ready to transmit data table 16 powerdown status register function the powerdown modes are as follows. the first three bits are to be used individually rather than in combination with each other. the last bit pr3 can be used in combination with pr2 or by itself. pr0 and pr1 control the pcm adcs and dacs only. pr6 is not supported by the WM9703. write bit function pr0 pcm in adcs and input mux powerdown pr1 pcm out dacs powerdown pr2 analogue mixer powerdown (vref still on) pr3 analogue mixer powerdown (vref off) pr4 digital interface (ac-link) powerdown (external clock off) pr5 internal clock disable pr6 hp amp powerdown ? not supported eapd external amplifier powerdown table 17 powerdown control register function pr0 = 1 pr1 = 1 pr2 = 1 pr4 = 1 pr0 = 0 and adc = 1 default ready = 1 cold reset warm reset pr2 = 0 and anl = 1 pr1 = 0 and dac = 1 adcs off pr0 dacs off pr1 analogue off pr2 or pr3 digital i/f off pr4 shut off coda link normal figure 17 an example of the WM9703 powerdown/powerup flow
WM9703 production data pd rev 3.5 september 2001 26 figure 17 illustrates one example of a procedure to do a complete powerdown of the WM9703. from normal operation sequential writes to the powerdown register are performed to powerdown the WM9703 a piece at a time. after everything has been shut off (pr0 to pr3 set), a final write (of pr4) can be executed to shut down the WM9703?s digital interface (ac-link). the part will remain in sleep mode with all its registers holding their static values. to wake up the WM9703, the ac?97 controller will send a pulse on the sync line issuing a warm reset. this will restart the WM9703?s digital interface (resetting pr4 to 0). the WM9703 can also be woken up with a cold reset. a cold reset will cause a loss of values of the registers, as a cold reset will set them to their default states. when a section is powered back on, the powerdown control/status register index 26h should be read to verify that the section is ready (i.e. stable) before attempting any operation that requires it. alternatively if resetb is held low, all pr bits are held set so the device is held powered off until resetb is taken high again. pr1 = 1 pr2 = 1 pr4 = 1 adcs off pr0 dacs off pr1 analogue off pr2 or pr3 digital i/f off pr4 warm reset pr1 = 0 and dac = 1 pr2 = 0 and anl = 1 shut off coda link figure 18 the WM9703 powerdown/flow with analogue still alive figure 18 illustrates a state when all the mixers should work with the static volume settings that are contained in their associated registers. this is used when the user is playing a cd (or external linein source) through WM9703 to the speakers but has most of the system in low power mode. the procedure for this follows the previous except that the analogue mixer is never shut down. powerdown control/status register (index 26h) note that in order to go into ultimate low power mode, pr5 is required to be set which turns off the oscillator circuit. asserting sync resets the pr5 bit and re-starts the oscillator in the same was as the ac link is restarted. also when resetb pin is asserted low, all pr bits are over-ridden and the entire device is powered off to ultra low power state for as long as resetb = low. on releasing resetb, the device is reset (all active) and powered up. revision 2.1 registers (index 28h t0 58h) these registers are specified as to use in revision 2.1 of the ac?97 specification and have the following functions on the WM9703: register 28h ? extended audio id the extended audio id register is a read only register that identifies which extended audio features are supported (in addition to the original ac?97 features identified by reading the reset register at index 00h). a non zero value indicates the feature is supported.
WM9703 production data pd rev 3.5 september 2001 27 data bit function any mode vra variable rate audio support 1 dra double rate audio support 0 vrm variable rate mic adc support 0 cdac centre dac support 0 sdac surround dac support 0 ldac lfe dac support 0 amap slot to front dac mapping support 1 id1 codec configuration ? pin 45 value inverse of level at pin 45 id0 codec configuration ? pin 46 value inverse of level at pin 46 table 18 extended audio capability register register 2ah ? extended audio status and control register the extended audio status and control register is a read/write register that provides status and control of the extended audio features. data bit function read/write WM9703 support vra enables variable rate audio mode read/write yes dra enable double rate audio mode read/write no vrm enables variable rate mic adc read/write no cdac indicates centre dac ready read yes sdac indicates surround dac ready read yes ldac indicates lfe dac ready read yes madc indicates mic adc ready read no pri set to turn off centre dac read/write enable only prj set to turn off surround dacs read/write enable only prk set to turn off lfe dacs read/write enable only prl set to turn off mic adc read/write no table 19 extended audio status and control register register 2ch to 32h ? audio sample rate control registers these registers are read/write registers that are written to, to select alternative sample rates for the audio pcm converters. default is the 48ks/s rate. note that only revision 2.1 recommended rates are supported by the WM9703, selection of any other unsupported rates will cause the rate to default to the nearest supported rate, and the supported rate value to be latched and so read back. register 2ch is the front dac rate register, but is also used for centre channel data rate. registers 36h and 38h ? 6 channel volume control these read/write registers control the output volume of the optional four pcm channels. (not supported by the WM9703) vendor reserved registers (index 5ah and 7ah) these registers are vendor specific. do not write to these registers unless the vendor id register has been checked first to ensure that the driver knows the source of the ac ?97 component. vendor specific gain control registers ? (index 70h to 74h) not used in the WM9703. vendor id registers (index 7ch to 7eh) this register is for specific vendor identification if so desired. the id method is microsoft?s plug and play vendor id code. the first character of that id is f7 to f0, the second character s7 to s0, and the third t7 to t0. these three characters are ascii encoded. the revision7 to revision0 field is for the vendor revision number. in the WM9703 the vendor id is set to wml3. wolfson is a registered microsoft plug and play vendor.
WM9703 production data pd rev 3.5 september 2001 28 serial interface register map the following table shows the function and address of the various control bits that are loaded through the serial interface during write operations. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset x se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 6150h 02h master volume mute x x ml4 ml3 ml2 ml1 ml0 x x x mr4 mr3 mr2 mr1 mr0 8000h 04h lnlvl volume mute x x ml4 ml3 ml2 ml1 ml0 x x x mr4 mr3 mr2 mr1 mr0 8000h 06h master volume mono mutexxxxxxxxxxmm4mm3mm2mm1mm0 8000h 0ah pcbeep volume mute x xxxxxxxxxpv3pv2pv2pv0x 8000h 0ch phone volume mute x xxxxxxxxxgn4gn3gn2gn1gn0 8008h 0ehmic volume mutexxxxxxxx 20db x gn4 gn3 gn2 gn1 gn0 8008h 10h line in volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 12h cd volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 14h video volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 16h aux volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 18h pcm out volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 1ahrec select xxxxxsl2sl1sl0xxxxxsr2sr1sr0 0000h 1ch rec gain mute x x x gl3 gl2 gl1 gl0 x x x x gr3 gr2 gr1 gr0 8000h 20h general purpose pop st 3d ld x x mix ms lpbk xxxxxx x 0000h 22h3d control xxxxxxxxxxxxdp3dp2dp1dp0 0000h 24hreserved xxxxxxxxxxxxxxx x 0000h 26h power/down control status eapd x pr5 pr4 pr3 pr2 pr1 pr0 x x x x ref anl dac adc 000fh 28h ext?d audio id id1 id0 xxxxamap ldac sdac cdac x x vrm x dra vra 0201h 2ah ext?d audio stat/ctrl x prl prk prj pri x madc ldac sdac cdac x x vrm x dra vra 0000h 2ch front dac rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 32h audio adc rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 72h front mixer volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 0808h 74h surround sound x x xxxxxxxxxxxxx x 0000h 7ah vendor reserved x x xxxxxxxxxxxxx x 0000h 7ch vendor id1 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 574dh 7eh vendor id2 t7 t6 t5 t4 t3 t2 t1 t0 rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 4c03h table 21 serial interface register map description
WM9703 production data pd rev 3.5 september 2001 29 recommended external components 1 9 4 7 dvdd1 dvdd2 dvss1 dvss2 25 38 26 42 27 28 29 31 33 34 vref vrefout afilt1 cap1 cx3d1 cx3d2 avss2 avss1 avdd2 avdd1 WM9703 dvdd avdd stereo output dgnd agnd 32 cap2 agnd agnd agnd 35 lineoutl 36 lineoutr 37 monoout 39 lnlvloutl 41 lnlvloutr line level stereo 43 nc 44 nc 48 nc 47 eapd xtlout 3 xtlin 2 pcbeep 12 phone 13 auxl 14 auxr 15 videol 16 videor 17 cdl 18 cdgnd 19 cdr 20 mic1 21 mic2 22 lineinl 23 lineinr 24 nc 30 nc 40 cid1 46 cid2 45 avss master/ slave control mixer inputs sdataout 5 bitclk 6 sdatain 8 sync 10 resetb 11 ac-link mono output dgnd c3 c4 c18 c19 c20 c21 c22 c23 c25 c24 c26 c27 c28 c29 c30 c31 c32 c33 c35 xt c34 c17 c16 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c2 c1 notes: 1. pins 27, 29 and 31 are internally connected. it is recommended that capacitors only be connected to one of these pins. 2. c1 to c28 should be as close to wm9704q as possible. 3. agnd and dgnd should be connected as close to wm9704q as possible. + + + + + + + + ++ + figure 19 external components diagram
WM9703 production data pd rev 3.5 september 2001 30 recommended external components values component reference suggested value description c1 to c4 10nf de-coupling for dvdd and avdd c5 to c17 470nf ac coupling capacitors for setting dc level of analogue inputs to vcap1. value chosen to give corner frequency below 20hz for min 10k input impedance. c18 1 f c19 0.1 f c20 10 f c21 0.1 f c22 10 f c23 0.1 f c24 10 f c25 0.1 f c26 10 f reference de-coupling capacitors for adc, dac, mixer and cap2 references. ceramic type or similar. c27 100nf 3d low pass filter. this value sets nominal 100hz. c28 47nf 3d high pass filter. this value sets nominal 1khz. c29 to c33 10 f output ac coupling caps to remove vref dc level from outputs. c34 and c35 22pf optional capacitors for better crystal frequency stability. xt 24.576 mhz ac?97 master clock frequency. a bias resistor is not required, but if connected will not affect operation if value is large (above 1m ? ). table 24 external component values recommendations for 3.3v operation the device?s performance with avdd = 3.3v is shown in electrical characteristics. in 3.3v analogue operation, mid-rail reference scales to 1.5v. all adc and dac references are 3/5 ths of their nominal 5v value. input and output signals that are 1vrms in 5v applications, scale to 660mvrms in 3.3v applications. if 1vrms output is required, the mixer gain adjust pgas need to be increased by 3 times 1.5db steps.
WM9703 production data pd rev 3.5 september 2001 31 package dimensions notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.25mm. d. meets jedec.95 ms-026, variation = bbc. refer to this specification for further details. dm003.b ft: 48 pin tqfp (7 x 7 x 1.4 mm) symbols dimensions (mm) min nom max a ----- ----- 1.60 a 1 0.05 ----- 0.15 a 2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 ----- 0.20 d 9.00 bsc d 1 7.00 bsc e 9.00 bsc e 1 7.00 bsc e 0.50 bsc l 0.45 0.60 0.75 0 o 3.5 o 7 o tolerances of form and position ccc 0.08 ref: jedec.95, ms-026 25 36 e b 12 1 d1 d e1 e 13 24 37 48 a a2 a1 seating plane ccc c -c- c l
WM9703 production data pd rev 3.5 september 2001 32 important notice wolfson microelectronics ltd (wm) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, tha t information being relied on is current. all products are sold subject to the wm terms and conditions of sale supplied at the ti me of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. wm warrants performance of its products to the specifications applicable at the time of sale in accordance with wm?s standard warranty. testing and other quality control techniques are utilised to the extent wm deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. in order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. wm assumes no liability for applications assistance or customer product design. wm does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual proper ty right of wm covering or relating to any combination, machine, or process in which such products or services might be or are used. wm?s publication of information regarding any third party?s products or services does not constitute wm?s approval, license, warrant y or endorsement thereof. reproduction of information from the wm web site or datasheets is permissable only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this informati on with alteration voids all warranties provided for an associated wm product or service, is an unfair and deceptive business prac tice, and wm is not responsible nor liable for any such use. resale of wm?s products or services with statements different from or beyond the parameters stated by wm for that product or service voids all express and any implied warranties for the associated wm product or service, is an unfair and deceptive busin ess practice, and wm is not responsible nor liable for any such use. address: wolfson microelectronics ltd 20 bernard terrace edinburgh eh8 9nx united kingdom tel :: +44 (0)131 667 9386 fax :: +44 (0)131 667 5176 email :: sales@wolfsonmicro.com

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